Zet status

IBM PC SOC system

This is the status of the different components of the IBM PC SoC:

module	status	comments
8086 CPU	almost	See section Zet processor for details
BIOS	partial	See BIOS status
Mem Cntrlr	done	Full RAM/ROM support read/write 8/16 bit even/odd addr, using the Intel memory map.
8237 DMA	no	Some information about the 8237 DMA controller.
8254 PIT	basic	We have the 8254 Timer from opencores.
8259A PIC	basic	There's no free core available. Here is the original Intel datasheet.
VDU	done	80x25 video text mode with blink/background/foreground attributes
16550 UART	partial	We have the 16550 UART from opencores.
8042 Keyb	basic	Basic functionality already implemented (interrupts, extended and release scan codes). Full specification.

Zet processor

Only the 16-bit part is implemented now. Here's an explanation of which features are implemented.

Instructions

From the total of 92 instructions that the 8086 has, 89 are implemented and they pass the corresponding test benches, as can be seen below. The 3 instructions left: wait, esc and lock are not going to be implemented because we are not using any coprocessor and thus are not needed.

Data transfer instructions

insn	status	comments
mov	done	See the Jmp/mov test bench, examples 1 to 12
push/pop	done	See the data transfer test bench, examples 6 to 8 and 10 to 12
in/out	done	See the data transfer test bench, examples 19 to 26
lahf/sahf	done	See the data transfer test bench, examples 1 and 2
lds/lea/les	done	See the data transfer test bench, examples 3, 4 and 5
pushf/popf	done	See the data transfer test bench, examples 9 and 13
xchg	done	See the data transfer test bench, examples 14 to 17
xlat	done	See the data transfer test bench, example 18

Arithmetic instructions

insn	status	comments
aaa/aas	done	See the Conversion instructions test bench, examples 1 to 10
aam	done	See the Division test bench, examples 25 to 30
aad	done	See the Multiplication test bench, examples 25 to 28
daa/das	done	See the Conversion instructions test bench, examples 11 to 24
cbw/cwd	done	See the Conversion instructions test bench, examples 25 to 30
inc	done	See the Addition instructions test bench, examples 29 to 34
dec	done	See the Subtraction instructions test bench, examples 29 to 34
add/adc	done	See the Addition instructions test bench, examples 1 to 28
sub/sbb	done	See the Subtraction instructions test bench, examples 1 to 28
mul/imul	done	See the Multiplication test bench, examples 1 to 24
div/idiv	done	See the Division test bench, examples 1 to 24
neg	done	See the Cmp/neg test bench, examples 15 to 22
cmp	done	See the Cmp/neg test bench, examples 1 to 14

Bitwise handling instructions

insn	status	comments
and/or	done	See the Bitwise test bench, examples 1 to 24
not	done	See the Bitwise test bench, examples 49 to 52
rcl	done	See the Rotate test bench, examples 1 to 8.
rcr	done	See the Rotate test bench, examples 9 to 16.
rol	done	See the Rotate test bench, examples 17 to 24.
ror	done	See the Rotate test bench, examples 25 to 32.
sal/shl	done	See the Shift test bench, examples 1 to 8
sar	done	See the Shift test bench, examples 9 to 16
shr	done	See the Shift test bench, examples 17 to 24
test	done	See the Bitwise test bench, examples 37 to 48
xor	done	See the Bitwise test bench, examples 25 to 36

Control transfer instructions

insn	status	comments
call	done	See the Jump instructions test bench 2, examples 1 to 5
ja/jnbe	done	See the Jump instructions test bench 1, example 1.
jae/jnb/jnc	done	See the Jump instructions test bench 1, example 2.
jb/jnae/jc	done	See the Jump instructions test bench 1, example 3.
jbe/jna	done	See the Jump instructions test bench 1, example 4.
jcxz	done	See the Jump instructions test bench 2, example 13.
je/jz	done	See the Jump instructions test bench 1, example 5.
jg/jnle	done	See the Jump instructions test bench 1, example 6.
jge/jnl	done	See the Jump instructions test bench 1, example 7.
jl/jnge	done	See the Jump instructions test bench 1, example 8.
jle/jng	done	See the Jump instructions test bench 1, example 9.
jne/jnz	done	See the Jump instructions test bench 1, example 10.
jno	done	See the Jump instructions test bench 1, example 11.
jnp/jpo	done	See the Jump instructions test bench 1, example 12.
jns	done	See the Jump instructions test bench 1, example 13.
jmp	done	See the Jmp/mov test bench, examples 1 to 5 (jmp).
jo	done	See the Jump instructions test bench 1, example 14.
jp/jpe	done	See the Jump instructions test bench 1, example 15.
js	done	See the Jump instructions test bench 1, example 16.
loop	done	See the Jump instructions test bench 2, example 6.
loope/loopz	done	See the Jump instructions test bench 2, example 7.
loopne/loopnz	done	See the Jump instructions test bench 2, example 8.
ret	done	See the Jump instructions test bench 2, examples 9 to 12.

String handling instructions

insn	status	comments
cmpsb/cmpsw	done	See the String instructions test bench, examples 1 and 2.
lodsb/lodsw	done	See the String instructions test bench, examples 3 and 4.
movsb/movsw	done	See the String instructions test bench, examples 5 and 6.
rep (pref)	done	See the String repeating prefixes test bench
repe/repz (pref)	done	See the String repeating prefixes test bench
repne/repnz (pref)	done	See the String repeating prefixes test bench
scasb/scasw	done	See the String instructions test bench, examples 7 and 8.
stosb/stosw	done	See the String instructions test bench, examples 9 and 10.

Interrupt instructions

insn	status	comments
int	done	See the Interrupt instructions test bench, examples 1 and 2.
into	done	See the Interrupt instructions test bench, example 3.
iret	done	See the Interrupt instructions test bench, example 4.

Microprocessor control instructions

insn	status	comments
clc	done	See the Microprocessor control instructions test bench, example 1.
cld	done	See the Microprocessor control instructions test bench, example 2.
cli	done	See the Microprocessor control instructions test bench, example 3.
cmc	done	See the Microprocessor control instructions test bench, example 4.
esc	N/A	We are not implementing any coprocessor at the moment.
hlt	done	See the Microprocessor control instructions test bench, example 5.
lock	N/A	We are not implementing any coprocessor at the moment.
nop	done	See the Microprocessor control instructions test bench, example 6.
stc	done	See the Microprocessor control instructions test bench, example 7.
std	done	See the Microprocessor control instructions test bench, example 8.
wait	N/A	We are not implementing any coprocessor at the moment.

Other features

From these other features included in the 8086, the first priority is the segment override prefix.

feature	status	comments
segment override prefix	done	See the Segment override test bench
external interrupts	done	See the external interrupt microcode

Internal interrupts (exceptions)

exception	status	comments
0	done	Division exception (internal interrupt 0). See the Division test bench, examples 2, 3 and others
1	no	Trap exception (internal interrupt 1). Need to be implemented.
2	no	NMI. Need to be implemented, but not really needed in SoC environment.
3	done	Debug exception. Implemented by instruction int3.
4	done	Overflow exception. Implemented by instruction into.