Create a test

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We create a text file in the cores/zet/tests, named test.s:

.org 65280

# ==== START OF CODE ====
# Example:
movw $0x7654, %ax
movw $0x1, %bx
movw %ax, (%bx)
movw $0xf100, %dx
movw $0x1234, %ax
outw %ax, %dx
movw (1), %cx
movw %cx, %ax
outw %ax, %dx
# ==== END OF THE CODE ====
# It must be contained in 239 bytes

.org 65520
jmp start

.org 65535
.byte 0xff

Then we create the output file by doing:

make test.out
gcc ../../../src/tools/mifer.c -o mifer
./mifer test.out
cp test.dat ../../flash/bootrom.dat

Then you need to resynthesize the design and load it into the FPGA.