zet.aluzina.org

Hello all:
I want to add the usb core to this project,I am not sure what I shoud do,by the way,I wrote a simple testbanch to the kotku.v ,but it dose not work,so this is another question,thanks.

Are you familiar with www.opencores.org? If not, you should register there and you will find lots of open source verilog and VHDL projects. I know I have see listed there a couple of USB cores. I would suggest starting there.

adding something into the fpga to add USB is one thing, but what about the driver ?

ok,I will try,thanks,i have known opencores,i just want to know how to make the usb work in zet system,what should i do?

your USB Ip should have a WB interface
store your files under the zet tree /zet/cores/yourUSBip
and give your folder and the top level file the same name like ./yourUSBip/yourUSBip.v

then you could modify the wb_switch to get a new unused slave with priority less than the last one (currently S7 sdram) and connect your usb wb to this new slave port.

if i had finished the vga memory ported from external csram to SDRam, you could use s1 as this one will be freed once vga gets its framebuffer via fml

after adding your ip to the wb switch and giving it the correct adr space, you will need to add the toplevel exporting signals and then include the software driver ...

thank you for help,